Ganzvaders
This project is an FPGA-based 80’s retro video game. Ganzvaders is still in a preliminary state, but I have an early glimpse showing its use of several of my other FPGA projects – VGA generation, sprites, I2C controller interface, and a simplistic acceleration model.
The game is all FPGA, i.e. no HPS, no soft MCU, no frame buffer, just on-the-fly generation of a VGA signal 800×600 at 60 Hz (40MHz pixel clock) and gameplay also implemented in the FPGA. A fun example of what FPGAs can do.
Lots still to do, but a fair amount of basic functionality in place. A quick demo of the current state:
Related Projects:
This project builds on a number of other projects on this site, including:
- Image to Mem Tool
- I2C Master for NES Mini Controller
- UART Transmitter
- VGA Generator
- Flexible Sprite Generator
Some of these are already documented on this website and shared on GitHub. I’m working to post the others.
Present Status
- Generates VGA signals (RGB,hsync,vsync) for 800 x 600, 60 Hz, 40 MHz pixel clock, 6 bit color
- Has a Flexible Sprite Generator module that draws a sprite as the raster goes by. Can perform animations from strips of sprites, and vertically flip or horizontally flip sprites on the fly. Note that since there is no frame buffer, this is all about how the sprite data is read as we’re chasing the raster
- Generates full rotations of sprite ships from only 10 images, using the horiz/vert flip features above
- Communicates with two retro NES controllers over independent I2C buses, using two instantiations of the I2C Master for NES Mini Controller project
- Basic inertia, acceleration, and gravity simulation
- Cheesy looking Earth image (790 x 65 pixels), converted from PNG to MEM (like all graphics in this game) using my Image to MEM tool and painted using the same Flexible Sprite Generator
- The red, green, blue bars and the ugly lunar lander in the upper left are leftovers from some test code I haven’t ripped out yet
Quartus Setup
For now, the top-level entity is a Quartus schematic file, but all real code is Verilog and will be shared once it’s a bit further along.