{"id":1619,"date":"2020-12-29T20:19:53","date_gmt":"2020-12-29T20:19:53","guid":{"rendered":"http:\/\/box2281.temp.domains\/~ganzwork\/?page_id=1619"},"modified":"2022-01-29T19:37:47","modified_gmt":"2022-01-29T19:37:47","slug":"uart-tx","status":"publish","type":"page","link":"https:\/\/ganslermike.com\/?page_id=1619","title":{"rendered":"UART TX"},"content":{"rendered":"\n

This short Verilog<\/a> project is intended for basic communications or as a debug tool for other larger projects. It implements a UART<\/a> transmitter at a selectable baud rate<\/a>, with the common “8N1<\/a>” (8 data bits, no parity, 1 stop bit) format.<\/p>\n\n\n\n

\"\"<\/a><\/figure><\/div>\n\n\n\n

I developed this on a Terasic DE10-Lite board<\/a>, which has an Altera MAX10<\/a> FPGA, using the Quartus Prime 20.1, Light Edition<\/a> toolchain. Outside of the I\/O mapping, nothing is really specific to this particular board or FPGA part, and the code can be easily adapted to other hardware.<\/p>\n\n\n\n

For Verilog<\/a> beginners, the project has examples of simple finite state machines<\/a>, case<\/a> statements, concatenation<\/a>, a synchronizer<\/a> or two, localparams<\/a>, module instantiation “by name”<\/a>, and a synthesizable<\/a> test module. <\/p>\n\n\n\n

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UART Basics<\/h3>\n\n\n\n

Ample discussions of UART communications can be found on allaboutcircuits.com<\/a>, Sparkfun<\/a>, and Wikipedia<\/a>, but I’l also point out a few highlights below. <\/p>\n\n\n\n

For the details on my implementation, the code is well commented so please check it out. The full Quartus project is up on my GitHub site<\/a> and the two relevant Verilog source files are also included at the bottom of this page.<\/p>\n\n\n\n

\"\"<\/a><\/figure><\/div>\n\n\n\n

Typical UART data framing<\/p>\n\n\n\n

A few few interesting UART<\/a> nuances to remember:<\/p>\n\n\n\n